Current-Mode PWM DC-DC Converters
16-PIN WIDE SO
12, 13, 14
4, 5, 6
Shutdown—active low. Connect to ground to power down chip; tie to V+ for normal
operation. Output voltage falls to 0V when
Reference Voltage Output (+1.23V) supplies up to 100µA for external loads.
Bypass to GND with a 0.047µF capacitor.
Soft-Start. Capacitor between SS and GND provides soft-start and
Compensation Capacitor Input externally compensates the outer (voltage)
feedback loop. Connect to OUT with a 330pF capacitor.
Output-Voltage Sense Input provides regulation feedback sensing.
Connect to +3.3V output.
Drain of internal P-channel power MOSFET*
Supply Voltage Input. Bypass to GND with 1µF ceramic and large-value
electrolytic capacitor in parallel. The 1µF capacitor must be as close
to the GND and V+ pins as possible.*
No Connect—no internal connections to these pins.
*16-pin wide SO package: All pins sharing the same name must be connected together externally.
The MAX748A/MAX763A switch-mode regulators use a
current-mode pulse-width-modulation (PWM) control
system in a step-down (buck) regulator topography.
They convert an unregulated DC input voltage from 4V
to 11V (MAX763A) or from 4V to 16V (MAX748A) to a
regulated 3.3V output at 300mA. For loads less than
300mA, V+ may be less than 4.0V (see the Output
Voltage vs. Supply Voltage graph in the
). The current-mode
PWM architecture provides cycle-by-cycle current limit-
ing, improved load-transient response, and simpler
The controller consists of two feedback loops: an inner
(current) loop that monitors the switch current via the
current-sense resistor and amplifier, and an outer (volt-
age) loop that monitors the output voltage through the
error amplifier (Figure 1). The inner loop performs
cycle-by-cycle current limiting, truncating the power
transistor on-time when the switch current reaches a
predetermined threshold. This threshold is determined
by the outer loop. For example, a sagging output volt-
age produces an error signal that raises the threshold,
allowing the circuit to store and transfer more energy
during each cycle.
Figure 2 shows a capacitor connected to the soft-start
(SS) pin to ensure orderly power-up. A typical value is
0.047µF. SS controls both the SS timing and the maxi-
mum output current that can be delivered while main-
The charging capacitor slowly raises the clamp on the
error-amplifier output voltage, limiting surge currents
at power-up by slowly increasing the cycle-by-cycle
current-limit threshold. Table 1 lists timing characteris-
tics for selected capacitor values and circuit conditions.
The overcurrent comparator trips when the load exceeds
approximately 1.2A. When either an undervoltage or over-
current fault condition is detected, an SS cycle is actively
initiated, which triggers an internal transistor to discharge
the SS capacitor to ground. An SS cycle is also enabled
at power-up and when coming out of shutdown mode.
The overcurrent comparator triggers when the load
current exceeds approximately 1.2A. On each clock
cycle, the output FET turns on and attempts to deliver
current until cycle-by-cycle or overcurrent limits are
exceeded. Note that the SS capacitor must be greater
than 0.01µF for overcurrent protection to function prop-
erly. A typical value is 0.047µF.