MAX708SESA Datasheet Download

Part No.:
MAX708SESA
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Download Datasheet
Description:
[+3V Voltage Monitoring, Low-Cost uP Supervisory Circuits]
File Size:
466 K
Page:
15 Pages
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Manufacturer:
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
PCB Prototype
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+3V Voltage Monitoring, Low-Cost µP
Supervisory Circuits
MAX706P/R/S/T, MAX706AP/AR/AS/AT, MAX708R/S/T
+3.3V
V
CC
+1V
V
RST
V
RST
t
RST
RESET
0V
+3.3V
RESET
0V
+3.3V
MR*
0V
t
RST
+12V
+3V/+3.3V
RESET
(RESET)
1MΩ
1%
V
CC
TO
µP
MAX706_
MAX708R/S/T
MR
PFI
GND
PFO
130kΩ
1%
t
MD
t
MR
*NOTE: MR EXTERNALLY DRIVEN LOW.
WDO TIMING SHOWN FOR MAX706P/R/S/T.
+3.3V
WDO*
0V
PARAMETER
MIN
TYP
10.87
MAX
11.50
UNIT
V
+12V RESET
10.24
THRESHOLD AT +25°C
( ) ARE FOR MAX706P/AP
Figure 3. RESET,
RESET
,
MR
, and
WDO
Timing
t
WP
t
WD
+3V/+3.3V
WDI
0V
+3V/+3.3V
WDO
0V
+3V/+3.3V
RESET
0V
RESET EXTERNALLY
TRIGGERED BY MR
t
RST
t
WD
t
WD
Figure 5. Monitoring Both +3V/+3.3V and +12V
MAX706R/S/T
MAX708R/S/T
MAX706AR/AS/AT
RESET
R1
Figure 4. MAX706AP/AR/AS/AT Watchdog Timing
WDO
can be connected to the nonmaskable interrupt
(NMI) input of a µP. When V
CC
drops below the reset
threshold,
WDO
immediately goes low, even if the
watchdog timer has not timed out (Figure 3). Normally,
this would trigger an NMI, but since reset is asserted
simultaneously, the NMI is overridden. The
WDO
should not be connected to
RESET
directly. Instead,
connect
WDO
to
MR
to generate a reset pulse when it
times out.
Figure 6.
RESET
Valid to GND Circuit
input pulse width is 500ns when V
CC
= +3V and 150ns
when V
CC
= +5V. Leave
MR
unconnected or connect
to V
CC
when not used.
Power-Fail Comparator
The power-fail comparator can be used for various pur-
poses because its output and noninverting input are
not internally connected. The inverting input is internally
connected to a 1.25V reference. The power-fail com-
parator has 10mV of hysteresis, which prevents repeat-
ed triggering of the power-fail output (PFO).
Manual Reset
The manual reset (MR) input allows
RESET
and RESET
to be activated by a pushbutton switch. The switch is
effectively debounced by the 140ms minimum reset
pulse width.
MR
can be driven by an external logic line
since it is TTL/CMOS compatible. The minimum
MR
8
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