Microprocessor Supervisory Circuits
Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not
used, connect to GND.
Output Supply Voltage. When V
is greater than VBATT and above the reset threshold, V
. When V
falls below VBATT and is below the reset threshold, V
connects to VBATT. Connect a 0.1µF
capacitor from V
to GND. Connect V
if no backup battery is used.
Input Supply Voltage, 5V input.
Ground. 0V reference for all signals.
Battery On Output. When V
switches to VBATT, BATT ON goes high. When V
switches to V
BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for V
ments greater than 250mA.
LOW LINE LOW LINE
output goes low when V
falls below the reset threshold. It returns high as soon as V
the reset threshold.
External Oscillator Input. When OSC SEL is unconnected or driven high, a 10µA pull-up connects from V
OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast
and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may
be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3).
Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and
OSC SEL watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1).
OSC SEL has a 10µA internal pull-up.
Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V,
goes low. When PFI is not used, connect PFI to GND or V
Power-Fail Output. This is the output of the power-fail comparator.
goes low when PFI is less than 1.25V.
This is an uncommitted comparator, and has no effect on any other internal circuitry.
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time-
goes low and reset is asserted for the reset timeout period.
remains low until the next tran-
sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage
divider between V
and GND, which sets it to mid-supply when left unconnected.
OUT goes low only when
IN is low and V
is above the reset threshold. If CE IN is
low when reset is asserted,
OUT will stay low for 15µs or until
IN goes high, whichever occurs first.
Chip-Enable Input. The input to chip-enable gating circuit. If
IN is not used, connect
IN to GND or V
Watchdog Output. If WDI remains high or low longer than the watchdog timeout period,
goes low and reset
is asserted for the reset timeout period.
returns high on the next transition at WDI.
remains high if
WDI is unconnected.
Output goes low whenever V
falls below the reset threshold.
will remain low typically for
200ms after V
crosses the reset threshold on power-up.
RESET is an active-high output. It is open drain, and the inverse of
–— — –
R E S E T and RESET Outputs
and RESET outputs ensure that the µP (with reset
inputs asserted either high or low) powers up in a
known state, and prevents code-execution errors dur-
ing power-down or brownout conditions.
output is active low, and typically sinks
3.2mA at 0.1V saturation voltage in its active state.
sources 1.6mA at typically
- 0.5V. RESET output is open drain, active high,
and typically sinks 3.2mA with a saturation voltage of
0.1V. When no backup battery is used,
guaranteed to be valid down to V
= 1V, and an
external 10kΩ pull-down resistor on
that it will be valid with V
down to GND (Figure 1).
goes below 1V, the gate drive to the
output switch reduces accordingly, increasing the
and the saturation voltage. The 10kΩ pull-
down resistor insures the parallel combination of switch
plus resistor is around 10kΩ and the output saturation
voltage is below 0.4V while sinking 40µA. When using
a 10kΩ external pull-down resistor, the high state for
output with V
= 4.75V will be 4.5V typical.
For battery voltages
2V connected to VBATT, RESET
remain valid for V
from 0V to 5.5V.