W320-04H Datasheet Download

Part No.:
W320-04H
Download:
Download Datasheet
Description:
[200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs]
File Size:
266 K
Page:
18 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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W320-04
200-MHz Spread Spectrum Clock Synthesizer/Driver
with Differential CPU Outputs
2W320-04
Features
Benefits
• Compliant with Intel
®
CK-Titan clock synthesizer/driver Supports next-generation Pentium
®
processors using
specifications
differential clock drivers
• Multiple output clocks at different frequencies
— Three pairs of differential CPU outputs, up to 200 MHz
— Ten synchronous PCI clocks, three free-running
— Six 3V66 clocks
— Two 48-MHz clocks
— One reference clock at 14.318 MHz
— One VCH clock
• Spread Spectrum clocking (down spread)
• Power-down features (PCI_STOP#, CPU_STOP#
PWR_DWN#)
• Three Select inputs (Mode select and IC Frequency
Select)
• OE and Test Mode support
• 56-pin SSOP package and 56-pin TSSOP package
Enables reduction of electromagnetic interference (EMI)
and overall system cost
Enables ACPI-compliant designs
Supports up to four CPU clock frequencies
Enables ATE and “bed of nails” testing
Widely available standard package enables lower cost
Motherboard clock generator
— Supports multiple CPUs and a chipset
— Support for PCI slots and chipset
— Supports AGP, DRCG reference, and Hub Link
— Supports USB host controller and graphic controller
— Supports ISA slots and I/O chip
Logic Block Diagram
VDD_REF
PWR
Pin Configurations
SSOP and TSSOP
Top View
REF
S1
S0
CPU_STOP#
CPU0
CPU#0
VDD_CPU
CPU1
CPU#1
GND_CPU
VDD_CPU
CPU2
CPU#2
MULT0#
IREF
GND_IREF
S2
USB
DOT
VDD_ 48 MHz
GND_ 48 MHz
3V66_1/VCH
PCI_STOP#
3V66_0
VDD_3V66
GND_3V66
SCLK
SDATA
X1
X2
XTAL
OSC
VDD_REF
XTAL_IN
XTAL_OUT
GND_REF
PCI_F0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
PLL Ref Freq
PLL 1
S0:2
Gate
PWR_GD#
CPU_STOP#
Divider
Network
PWR
Stop
Clock
Control
VDD_CPU
CPU0:2
CPU#0:2
PCI_F1
PCI_F2
VDD_PCI
GND_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
PWR
Stop
Clock
Control
VDD_PCI
PCI_F0:2
PCI0:6
PCI_STOP#
/2
PWR_DWN#
PWR
VDD_3V66
3V66_0
3V66_2:4/
66BUFF0:2
3V66_5/ 66IN
GND_PCI
PCI4
PCI5
PCI6
VDD_3V66
GND_3V66
66BUFF0/3V66_2
66BUFF1/3V66_3
66BUFF2/3V66_4
66IN/3V66_5
PWR_DWN#
VDD_CORE
GND_CORE
PWR_GD#
PWR
PLL 2
VDD_48MHz
PWR
USB (48MHz)
DOT (48MHz)
VCH_CLK/ 3V66_1
SDATA
SCLK
SMBus
Logic
Cypress Semiconductor Corporation
Document #: 38-07010 Rev. *B
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised January 8, 2002
W320-04
14