CY8C29866-24AXI Datasheet Download

Part No.:
CY8C29866-24AXI
Download:
Download Datasheet
Description:
[PSoC® Mixed-Signal Array]
File Size:
632 K
Page:
49 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY8C29866-24AXI Datasheet Page:2CY8C29866-24AXI Datasheet Page:3CY8C29866-24AXI Datasheet Page:4CY8C29866-24AXI Datasheet Page:5CY8C29866-24AXI Datasheet Page:6CY8C29866-24AXI Datasheet Page:7CY8C29866-24AXI Datasheet Page:8CY8C29866-24AXI Datasheet Page:9 
PSoC® Mixed-Signal Array
CY8C29466, CY8C29566,
CY8C29666, and CY8C29866
Final Data Sheet
Features
Powerful Harvard Architecture Processor
M8C Processor Speeds to 24 MHz
Two 8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
3.0V to 5.25V Operating Voltage
Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
Industrial Temperature Range: -40°C to +85°C
Advanced Peripherals (PSoC Blocks)
12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
16 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 4 Full-Duplex UARTs
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
Precision, Programmable Clocking
Internal ±2.5% 24/48 MHz Oscillator
24/48 MHz with Optional 32.768 kHz Crystal
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
Flexible On-Chip Memory
32K Bytes Flash Program Storage 50,000
Erase/Write Cycles
2K Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
Programmable Pin Configurations
25 mA Sink on all GPIO
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 12 Analog Inputs on GPIO
Four 40 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
Additional System Resources
I
2
C™ Slave, Master, and Multi-Master to
400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
Complete Development Tools
Free Development Software
(PSoC Designer™)
Full-Featured, In-Circuit Emulator and
Programmer
Full Speed Emulation
Complex Breakpoint Structure
128K Bytes Trace Memory
Complex Events
C Compilers, Assembler, and Linker
Port 7 Port 6
Port 5
Port 4 Port 3
Port 2
Port 1
Port 0
Analog
Drivers
PSoC® Functional Overview
The PSoC® family consists of many
Mixed-Signal Array with
On-Chip Controller
devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C29x66 family can have up to eight IO
ports that connect to the global digital and analog interconnects,
providing access to 16 digital blocks and 12 analog blocks.
SYSTEM BUS
Global Digital Interconnect
SRAM
2K
Interrupt
Controller
Global Analog Interconnect
Flash 32K
SROM
PSoC CORE
Sleep and
Watchdog
CPUCore (M8C)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Ref.
Analog
Block
Array
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
processor. The CPU utilizes an interrupt controller with 25 vec-
Digital
Clocks
Two
Multiply
Accums.
POR and LVD
Decimator
I
2
C
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
August 5, 2008
© Cypress Semiconductor 2003-2008 — Document No. 38-12013 Rev. *J
1