CY8C29466-24PVXI Datasheet Download

Part No.:
CY8C29466-24PVXI
Download:
Download Datasheet
Description:
[PSoC Programmable System-on-Chip]
File Size:
1401 K
Page:
46 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY8C29466, CY8C29566
CY8C29666, CY8C29866
8.2 44-Pin Part Pinout
Table 8-2. 44-Pin Part Pinout (TQFP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Type
Digital Analog
IO
IO
I
IO
I
IO
IO
IO
IO
Power
IO
IO
IO
IO
IO
IO
IO
IO
Power
IO
IO
IO
IO
IO
IO
IO
IO
Input
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Power
IO
IO
IO
IO
IO
I
IO
IO
I
Pin
Name
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
Description
Direct switched capacitor block input.
Direct switched capacitor block input.
Figure 8-2. CY8C29566 44-Pin PSoC Device
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6],ExternalVREF
33
32
31
30
29
28
27
26
25
24
23
P2[4],External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull
down.
I
I
I
IO
IO
I
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VREF).
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
LEGEND:
A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the
PSoC Programmable System-on-ChipTechnical Reference Manual
for details.
Document Number: 38-12013 Rev. *K
P3[1]
I2CSCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2CSCL,XTALin,P1[1]
Vss
I2CSDA,XTALout,P1[0]
P1[2]
EXTCLK,P1[4]
P1[6]
P3[0]
12
13
14
15
16
17
18
19
20
21
22
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
P2[7]
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
Vdd
TQFP
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