CY8C24794-24LFXI Datasheet Download

Part No.:
CY8C24794-24LFXI
Download:
Download Datasheet
Description:
[PSoC Programmable System-on-Chip]
File Size:
1479 K
Page:
47 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY8C24094, CY8C24794
CY8C24894, CY8C24994
PSoC
®
Programmable System-on-Chip™
1. Features
XRES Pin to Support In-System Serial Programming (ISSP)
and External Reset Control in CY8C24894
Powerful Harvard Architecture Processor
M8C Processor Speeds to 24 MHz
Two 8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
3V to 5.25V Operating Voltage
Industrial Temperature Range: -40°C to +85°C
USB Temperature Range: -10°C to +85°C
Advanced Peripherals (PSoC
®
Blocks)
6 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPI/O Pins
Complex Peripherals by Combining Blocks
Capacitive Sensing Application Capability
Full Speed USB (12 Mbps)
Four Uni-Directional Endpoints
One Bi-Directional Control Endpoint
USB 2.0 Compliant
Dedicated 256 Byte Buffer
No External Crystal Required
Flexible On-Chip Memory
16K Flash Program Storage 50,000 Erase and Write Cycles
1K SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
Programmable Pin Configurations
25 mA Sink, 10 mA Drive on all GPI/O
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPI/O
Up to 48 Analog Inputs on GPI/O
Two 33 mA Analog Outputs on GPI/O
Configurable Interrupt on all GPI/O
Precision, Programmable Clocking
Internal ±4% 24 and 48 MHz Oscillator
Internal Oscillator for Watchdog and Sleep
0.25% Accuracy for USB with no External Components
Additional System Resources
2
I C Slave, Master, and Multi-Master to 400 kHz
Watchdog and Sleep Timers
User Configurable Low Voltage Detection
P o rt 3
P o rt 2
P o rt 1
P o rt 0
A n a lo g
D r iv e r s
2. Logic Block Diagram
System Bus
P o rt 7
P o rt 5
P o rt 4
G lo b a l D ig ita l In t e r c o n n e c t
G lo b a l A n a lo g In te r c o n n e c t
F la s h 1 6 K
S le e p a n d
W a tc h d o g
PSoC C O R E
SR AM
1K
In te rru p t
C o n tr o lle r
SR O M
C P U C o re (M 8 C )
C lo c k S o u r c e s
( I n c lu d e s IM O a n d I L O )
D IG IT A L
S Y S TEM
A N A LO G
A n a lo g
B lo c k
A rra y
SYSTEM
A n a lo g
R e f.
D ig ita l
B lo c k
A rra y
D ig ita l
C lo c k s
2
M AC s
D e c im a to r
Type 2
I2 C
PO R and LVD
S y s te m R e s e ts
In te rn a l
V o lta g e
R e f.
U S B
A n a lo g
In p u t
M u x in g
SY S TE M R E S O U R C ES
Cypress Semiconductor Corporation
Document Number: 38-12018 Rev. *O
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 11, 2009