CY8C27243-24PVXI Datasheet Download

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CY8C27243-24PVXI
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Download Datasheet
Description:
[PSoC Mixed Signal Array]
File Size:
543 K
Page:
44 Pages
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Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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PSoC™ Mixed Signal Array
CY8C27143, CY8C27243,
CY8C27443, CY8C27543, and CY8C27643
Final Data Sheet
Features
Powerful Harvard Architecture Processor
M8C Processor Speeds to 24 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
3.0 to 5.25 V Operating Voltage
Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
Industrial Temperature Range: -40°C to +85°C
Advanced Peripherals (PSoC Blocks)
12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
8 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 2 Full-Duplex UARTs
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
Precision, Programmable Clocking
Internal 2.5% 24/48 MHz Oscillator
24/48 MHz with Optional 32 kHz Crystal
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
Flexible On-Chip Memory
16K Bytes Flash Program Storage 50,000
Erase/Write Cycles
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP™)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
Programmable Pin Configurations
25 mA Sink on all GPIO
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 12 Analog Inputs on GPIO
Four 30 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
Additional System Resources
I
2
C™ Slave, Master, and Multi-Master to
400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
Complete Development Tools
Free Development Software
(PSoC™ Designer)
Full-Featured, In-Circuit Emulator and
Programmer
Full Speed Emulation
Complex Breakpoint Structure
128K Bytes Trace Memory
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
PSoC™ Functional Overview
The PSoC™ family consists of many
Mixed Signal Array with
On-Chip Controller
devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C27x43 family can have up to five IO
ports that connect to the global digital and analog interconnects,
providing access to 8 digital blocks and 12 analog blocks.
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Interrupt
Controller
Global Analog Interconnect
Flash 16K
Sleep and
Watchdog
SROM
CPU Core (M8C)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
(2 Rows,
8 Blocks)
ANALOG SYSTEM
Analog
Block
Array
(4 Columns,
12 Blocks)
Analog
Ref
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
Digital
Clocks
Multiply
Accum.
POR and LVD
Decimator
I
2
C
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
August 3, 2004
© Cypress MicroSystems, Inc. 2002 – 2004 — Document No. 38-12012 Rev. *I
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