CY8C24223A-24PVXI Datasheet Download

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CY8C24223A-24PVXI
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Download Datasheet
Description:
[PSoC㈢ Mixed-Signal Array]
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735 K
Page:
55 Pages
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Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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PSoC® Mixed-Signal Array
CY8C24123A,
CY8C24223A, and CY8C24423A
Final Data Sheet
Features
Powerful Harvard Architecture Processor
M8C Processor Speeds to 24 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
2.4 to 5.25V Operating Voltage
Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
Industrial Temperature Range: -40°C to +85°C
Advanced Peripherals (PSoC Blocks)
6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
Precision, Programmable Clocking
Internal ±2.5% 24/48 MHz Oscillator
High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
Flexible On-Chip Memory
4K Flash Program Storage 50,000 Erase/Write
Cycles
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
Programmable Pin Configurations
25 mA Sink on all GPIO
Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 10 Analog Inputs on GPIO
Two 30 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
New CY8C24x23A PSoC Device
Derived from the CY8C24x23 Device
Low Power and Low Voltage (2.4V)
Additional System Resources
I
2
C™ Slave, Master, and Multi-Master to
400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
Complete Development Tools
Free Development Software
(PSoC Designer™)
Full-Featured, In-Circuit Emulator and
Programmer
Full Speed Emulation
Complex Breakpoint Structure
128K Trace Memory
Port 2 Port 1 Port 0
Analog
Drivers
PSoC® Functional Overview
The PSoC® family consists of many
Mixed-Signal Array with
On-Chip Controller
devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C24x23A family can have up to three IO
ports that connect to the global digital and analog interconnects,
providing access to 4 digital blocks and 6 analog blocks.
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Interrupt
Controller
Global Analog Interconnect
Flash 4K
Sleep and
Watchdog
SROM
CPU Core (M8C)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Ref
Analog
Block
Array
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
Digital
Clocks
Multiply
Accum.
Decimator
I
2
C
POR and LVD
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
October 17, 2006
© Cypress Semiconductor Corp. 2004-2006 — Document No. 38-12028 Rev. *F
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