CY7C67300-100AXI Datasheet Download

Part No.:
CY7C67300-100AXI
Download:
Download Datasheet
Description:
[EZ-Host Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support]
File Size:
1832 K
Page:
99 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C67300
SPI Pins
HSS Pins
The SPI port has a few different pin location options as shown in
The port location is selectable via the GPIO control
register [0xC006].
Table 9. SPI Interface Pins
Pin Name
Default Location
Pin Number
The HSS port has a few different pin location options as shown
in
The port location is selectable via the GPIO control
register [0xC006].
Table 10. HSS Interface Pins
Pin Name
Default Location
Pin Number
nSSI
SCK
MOSI
MISO
Alternate Location
56 or 65
61
60
66
73
72
71
74
CTS
RTS
RXD
TXD
Alternate Location
44
53
54
55
67
68
69
70
nSSI
SCK
MOSI
MISO
CTS
RTS
RXD
TXD
High-Speed Serial Interface
EZ-Host provides an HSS interface. The HSS interface is a
programmable serial connection with baud rate from 9600 baud
to 2.0M baud. The HSS interface supports both byte and block
mode operations and also hardware and software handshaking.
Complete control of EZ-Host can be accomplished through this
interface via an extensible API and communication protocol. The
HSS interface can be exposed through GPIO pins or the External
Memory port.
HSS Features
Programmable Pulse/PWM Interface
EZ-Host has four built in PWM output channels. Each channel
provides a programmable timing generator sequence that can be
used to interface to various image sensors or other applications.
The PWM interface is exposed through GPIO pins.
Programmable Pulse/PWM Features
Four independent programmable waveform generators
Programmable predefined frequencies ranging from 5.90 KHz
to 48 MHz
Configurable polarity
Continuous and one-shot mode available
8 bits, no parity code
Programmable baud rate from 9600 baud to 2M baud
Selectable 1- or 2-stop bit on transmit
Programmable inter-character gap timing for Block Transmit
8-byte receive FIFO
Glitch filter on receive
Block mode transfer directly to/from EZ-Host internal memory
(DMA transfer)
Selectable CTS/RTS hardware signal handshake protocol
Selectable XON/XOFF software handshake protocol
Programmable Receive interrupt, Block Transfer Done inter-
rupts
Complete access to internal memory
Programmable Pulse/PWM Pins.
Table 11. PWM Interface Pins
Pin Name
Pin Number
PWM3
PWM2
PWM1
PWM0
44
53
54
55
Document #: 38-08015 Rev. *J
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