EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first
USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is
designed to easily interface to most high-performance CPUs
to add USB host functionality. EZ-OTG has its own 16-bit RISC
processor to act as a coprocessor or operate in standalone
mode. EZ-OTG also has a programmable IO interface block
allowing a wide range of interface options.
EZ-OTG provides 128 interrupt vectors. The first 48 vectors
are hardware interrupts and the following 80 vectors are
General Timers and Watchdog Timer
EZ-OTG has two built-in programmable timers and a
watchdog timer. All three timers can generate an interrupt to
EZ-OTG has one main power-saving mode, Sleep. Sleep
mode pauses all operations and provides the lowest power
Processor Core Functional Overview
An overview of the processor core components are presented
in this section.
EZ-OTG has a general purpose 16-bit embedded RISC
processor that runs at 48 MHz.
EZ-OTG requires a 12 MHz source for clocking. Either an
external crystal or TTL-level oscillator may be used. EZ-OTG
has an internal PLL that produces a 48 MHz internal clock from
the 12 MHz source.
EZ-OTG has a built-in 4K × 16 masked ROM and an 8K × 16
internal RAM. The masked ROM contains the EZ-OTG BIOS.
The internal RAM can be used for program code or data.
Table 1. Interface Options for GPIO Pins
EZ-OTG has a variety of interface options for connectivity, with
several interface options available. See
how the interfaces share pins and can coexist. Below are
some general guidelines:
• I2C EEPROM and OTG do not conflict with any interfaces
• HPI is mutually exclusive to HSS, SPI, and UART
Document #: 38-08014 Rev. *G
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