CY7C63723-PC Datasheet Download

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[enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller]
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58 Pages
PCB Prototype
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USB CY7C63722/23
Functional Overview
USB - The New USB Standard
Cypress has re-invented its leadership position in the low-speed USB market with a new family of innovative microcontrollers.
Introducing...enCoRe USB—“enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to
create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a minimum
number of components. At the heart of the
USB technology is the breakthrough design of a crystal-less oscillator. By
integrating the oscillator into our chip, an external crystal or resonator is no longer needed. We have also integrated other external
components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator.
All of this adds up to a lower system cost.
The CY7C637xx is an 8-bit RISC One Time Programmable (OTP) microcontroller. The instruction set has been optimized specif-
ically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications.
The CY7C637xx features up to 16 general purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins
are grouped into two ports (Port 0 to 1) where each pin can be individually configured as inputs with internal pull-ups, open drain
outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each I/O pin can
be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector.
The CY7C637xx microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be set
to precisely tune to USB timing requirements (6 MHz ±1.5%). Optionally, an external 6-MHz ceramic resonator can be used to
provide a higher precision reference for USB operation. This clock generator reduces the clock-related noise emissions (EMI).
The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller.
The CY7C637xx has 8 Kbytes of EPROM and 256 bytes of data RAM for stack space, user variables, and USB FIFOs.
These parts include low-voltage reset logic, a watchdog timer, a vectored interrupt controller, a 12-bit free-running timer, and
capture timers. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state,
and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when V
drops below the operating
voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms.
The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB
Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, two capture timers, an internal
wake-up timer and the GPIO ports. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after
USB transactions complete on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO
edge event. The GPIO ports have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional
flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be
either rising or falling edge.
The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128
and 1.024 ms). The timer
can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event,
and subtracting the two values. The four capture timers save a programmable 8 bit range of the free-running timer when a GPIO
edge occurs on the two capture pins (P0.0, P0.1).
The CY7C637xx includes an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware
supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated
into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the D– pin.
The USB D+ and D– USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to
respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and
SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components
are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge
rates operate in both modes to reduce EMI.
Document #: 38-08022 Rev. **
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