CY7C421-40JC Datasheet Download

Part No.:
Download Datasheet
[256/512/1K/2K/4K x 9 Asynchronous FIFO]
File Size:
607 K
17 Pages
PCB Prototype
 CY7C421-40JC Datasheet Page:2CY7C421-40JC Datasheet Page:3CY7C421-40JC Datasheet Page:4CY7C421-40JC Datasheet Page:5CY7C421-40JC Datasheet Page:6CY7C421-40JC Datasheet Page:7CY7C421-40JC Datasheet Page:8CY7C421-40JC Datasheet Page:9 
CY7C419/21/25/29/33256/512/1K/2K/4K x 9 Asynchronous FIFO
256/512/1K/2K/4K x 9 Asynchronous FIFO
Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
600-mil wide and 300-mil wide packages. There are 256, 512,
1,024, 2,048, and 4,096 words respectively by 9 bits wide. Each
FIFO memory is organized such that the data is read in the same
sequential order that it was written. Full and empty flags are
provided to prevent overrun and underrun. Three additional pins
are also provided to facilitate unlimited expansion in width, depth,
or both. The depth expansion technique steers the control
signals from one device to another in parallel. This eliminates the
serial addition of propagation delays, so that throughput is not
reduced. Data is steered in a similar manner.
The read and write operations may be asynchronous; each can
occur at a rate of 50 MHz. The write operation occurs when the
write (W) signal is LOW. Read occurs when read (R) goes LOW.
The nine data outputs go to the high impedance state when R is
A Half Full (HF) output flag that is valid in the standalone and
width expansion configurations is provided. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it is
In the standalone and width expansion configurations, a LOW on
the retransmit (RT) input causes the FIFOs to retransmit the
data. Read enable (R) and write enable (W) must both be HIGH
during retransmit, and then R is used to access the data.
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated
using an advanced 0.65-micron P-well CMOS technology. Input
ESD protection is greater than 2000V and latch-up is prevented
by careful layout and guard rings.
Asynchronous first-in first-out (FIFO) buffer memories
256 x 9 (CY7C419)
512 x 9 (CY7C421)
1K x 9 (CY7C425)
2K x 9 (CY7C429)
4K x 9 (CY7C433)
Dual-ported RAM cell
High speed 50 MHz read and write independent of depth and
Low operating power: I
= 35 mA
Empty and full flags (Half Full flag in standalone)
TTL compatible
Retransmit in standalone
Expandable in width
PLCC, 7x7 TQFP, SOJ, 300-mil, and 600-mil DIP
Pb-free packages available
Pin compatible and functionally equivalent to IDT7200,
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 38-06001 Rev. *C
198 Champion Court
San Jose
CA 95134-1709
Revised December 09, 2008