CY7C4235-15AC Datasheet Download

Part No.:
CY7C4235-15AC
Download:
Download Datasheet
Description:
[64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs]
File Size:
411 K
Page:
25 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C4235-15AC Datasheet Page:4CY7C4235-15AC Datasheet Page:5CY7C4235-15AC Datasheet Page:6CY7C4235-15AC Datasheet Page:7CY7C4235-15AC Datasheet Page:9CY7C4235-15AC Datasheet Page:10CY7C4235-15AC Datasheet Page:11CY7C4235-15AC Datasheet Page:12 
CY7C4425/4205/4215
CY7C4225/4235/4245
Switching Waveforms
(continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D
0
–D
17
t
ENS
WEN
t
SKEW2
RCLK
t
REF
EF
t
FRL
[17]
D
0
(FIRSTVALID WRITE)
D
1
D
2
D
3
D
4
REN
t
A
Q
0
–Q
17
t
OLZ
t
OE
OE
42X5–9
t
A
D
0
[18]
D
1
Empty Flag Timing
WCLK
t
DS
D
0
–D
17
t
ENS
WEN
t
FRL[17]
RCLK
t
SKEW2
EF
t
REF
t
REF
t
SKEW2
t
REF
[17]
t
FRL
t
DS
D0
t
ENH
t
ENS
D1
t
ENH
REN
OE
t
A
Q
0
–Q
17
D0
42X5–10
Notes:
17. When t
SKEW2
> minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW2
. When t
SKEW2
< minimum specification, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW2
or t
CLK
+ t
SKEW2
.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
18. The first word is available the cycle after EF goes HIGH, always.
8