CY7C291A-35JC Datasheet Download

Part No.:
CY7C291A-35JC
Download:
Download Datasheet
Description:
[2K x 8 Reprogrammable PROM]
File Size:
270 K
Page:
12 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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92A
CY7C291A
2K x 8 Reprogrammable PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 20 ns (Commercial)
— 35 ns (Military)
Low power
— 660 mW (Commercial and Military)
Low standby power
— 220 mW (Commercial and Military)
EPROM technology 100% programmable
Slim 300-mil or standard 600-mil packaging available
5V
±10%
V
CC
, commercial and military
TTL-compatible I/O
Direct replacement for bipolar PROMs
Capable of withstanding >2001V static discharge
Functional Description
The CY7C291A is a high-performance 2K-word by 8-bit
CMOS PROM. It is packaged in a 300-mil ceramic package
which may be equipped with an erasure window; when
exposed to UV light the PROM is erased and can then be
reprogrammed. The memory cells utilize proven EPROM
floating-gate
technology
and
byte-wide
intelligent
programming algorithms.
The CY7C291A is a plug-in replacement for bipolar devices
and offers the advantage of lower power, reprogrammability,
superior performance and programming yield. The EPROM
cell requires only 12.5V for the supervoltage and low current
requirements allow for gang programming. The EPROM cells
allow for each memory location to be tested 100%, as each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that after customer programming the
product will meet DC and AC specification limits.
A read is accomplished by placing an active LOW signal on
CS
1
, and active HIGH signals on CS
2
and CS
3
. The contents
of the memory location addressed by the address line
(A
0
−A
10
) will become available on the output lines (O
0
−O
7
).
Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
O
3
A
8
A
9
A
10
COLUMN
ADDRESS
POWER
DOWN
7C293A
O
2
O
1
ADDRESS
DECODER
O
4
ROW
ADDRESS
PROGRAM-
MABLE
ARRAY
MULTI-
PLEXER
O
6
O
7
Pin Configurations
DIP
Top View
A
7
A
6
O
5
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
24
2
23
3 7C291A 22
4
21
5
20
6
19
18
7
8
17
9
16
10
15
11
14
12
13
V
CC
A
8
A
9
A
10
CS
1
CS
2
CS
3
O
7
O
6
O
5
O
4
O
3
LCC/PLCC (Opaque Only)
Top View
A5
A6
A7
NC
V
CC
A8
A9
A
4
A
3
A
2
A
1
A
0
NC
O
0
4 3 2 1 28 27 26
25
5
24
6
7C291A
23
7
22
8
21
9
20
10
19
11
12 1314151617 18
O1
O2
GND
NC
O3
O4
O5
A
10
CS
1
CS
2
CS
3
NC
O
7
O
6
O
0
CS
1
CS
2
CS
3
Window available
Cypress Semiconductor Corporation
Document #: 38-04011 Rev. *A
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised October 8, 2002