CY7C144-15AC Datasheet Download

Part No.:
CY7C144-15AC
Download:
Download Datasheet
Description:
[8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY]
File Size:
641 K
Page:
20 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C144, CY7C145
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
Features
Functional Description
The CY7C144 and CY7C145 are high speed CMOS 8K x 8 and
8K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C144/5 to handle situations when multiple
processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C144/5 can
be used as a standalone 64/72-Kbit dual-port static RAM or
multiple devices can be combined in order to function as a
16/18-bit or wider master/slave dual-port static RAM. An M/S pin
is provided for implementing 16/18-bit or wider memory applica-
tions without the need for separate master and slave devices or
additional discrete logic. Application areas include interpro-
cessor/multiprocessor
designs,
communications
status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags, BUSY
and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed
by the other port. The interrupt flag (INT) permits communication
between ports or systems by means of a mail box. The
semaphores are used to pass a flag, or token, from one port to
the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
R/W
R
CE
R
OE
R
True Dual-Ported Memory Cells that Enable Simultaneous
Reads of the same Memory Location
8K x 8 Organization (CY7C144)
8K x 9 Organization (CY7C145)
0.65-Micron CMOS for optimum Speed and Power
High Speed Access: 15 ns
Low Operating Power: I
CC
= 160 mA (max.)
Fully Asynchronous Operation
Automatic Power Down
TTL Compatible
Master/Slave Select Pin enables Bus Width Expansion to 16/18
Bits or more
Busy Arbitration Scheme provided
Semaphores included to permit Software Handshaking
between Ports
INT Flag for Port-to-Port Communication
Available in 68-pin PLCC, 64-pin and 80-pin TQFP
Pb-free Packages available
Logic Block Diagram
R/W
L
CE
L
OE
L
(7C145) I/O
8L
I/O
7L
I/O
0L
BUSY
L
I/O
CONTROL
I/O
CONTROL
I/O
8R
(7C145)
I/O
7R
I/O
0R
BUSY
R
A
12R
A
12L
A
0L
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A
0R
CE
L
OE
L
R/W
L
SEM
L
INT
L
INTERRUPT
SEMAPHORE
ARBITRATION
CE
R
OE
R
R/W
R
SEM
R
INT
R
M/S
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document #: 38-06034 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 26, 2009