CY7C185-35SC Datasheet Download

Part No.:
CY7C185-35SC
Download:
Download Datasheet
Description:
[64-Kbit (8 K × 8) Static RAM CMOS for optimum speed/power]
File Size:
380 K
Page:
15 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C185
64-Kbit (8 K × 8) Static RAM
Features
Functional Description
The CY7C185
is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), and active LOW output enable (OE) and
tri-state drivers. This device has an automatic power-down
feature (CE
1
or CE
2
), reducing the power consumption by 70%
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
1
and WE
inputs are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address pins
(A
0
through A
12
). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on the
eight data input or output pins.
The input or output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH. A die coat is used to insure alpha immunity.
High speed
15 ns
Fast t
DOE
Low active power
715 mW
Low standby power
85 mW
CMOS for optimum speed/power
Easy memory expansion with CE
1
, CE
2
and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin
(300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded
DIP
Logic Block Diagram
I/O
0
INPUT BUFFER
I/O
1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
8K x 8
ARRAY
CE
1
CE
2
WE
OE
COLUMN DECODER
POWER
DOWN
I/O
7
A
10
A
11
Selection Guide
Description
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
-15
15
130
15
-20
20
110
15
-35
35
100
15
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
www.cypress.com.
A
12
A
0
A
9
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 20, 2011