CY7C1370D-167AXC Datasheet Download

Part No.:
CY7C1370D-167AXC
Download:
Download Datasheet
Description:
[18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL? Architecture]
File Size:
462 K
Page:
28 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C1370D
CY7C1372D
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Operation
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Address
Used
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
CE
H
X
L
X
L
X
L
X
L
X
X
X
ZZ
L
L
L
L
L
L
L
L
L
L
L
H
ADV/LD
L
H
L
H
L
H
L
H
L
H
X
X
WE
X
X
H
X
H
X
L
X
L
X
X
X
BW
x
X
X
X
X
X
X
L
L
H
H
X
X
OE
X
X
L
L
H
H
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
X
CEN
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
DQ
Tri-State
Tri-State
Data Out (Q)
Data Out (Q)
Tri-State
Tri-State
Data In (D)
Data In (D)
Tri-State
Tri-State
Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW
X
. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ
s
and DQP
X
= Three-state when OE
is inactive or when the device is deselected, and DQ
s
= data when OE is active.
Document #: 38-05555 Rev. *F
Page 9 of 28