CY7C1370D-167AXC Datasheet Download

Part No.:
CY7C1370D-167AXC
Download:
Download Datasheet
Description:
[18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL? Architecture]
File Size:
462 K
Page:
28 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C1370D
CY7C1372D
Pin Definitions
Pin Name
A0
A1
A
BW
a
BW
b
BW
c
BW
d
WE
ADV/LD
I/O Type
Pin Description
Input-
Address Inputs used to select one of the address locations.
Sampled at the rising edge of
Synchronous the CLK.
Input-
Byte Write Select Inputs, active LOW.
Qualified with WE to conduct writes to the SRAM.
Synchronous Sampled on the rising edge of CLK. BW
a
controls DQ
a
and DQP
a
, BW
b
controls DQ
b
and DQP
b
,
BW
c
controls DQ
c
and DQP
c
, BW
d
controls DQ
d
and DQP
d
.
Input-
Write Enable Input, active LOW.
Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous signal must be asserted LOW to initiate a write sequence.
Input-
Advance/Load Input used to advance the on-chip address counter or load a new address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Input-
Clock
Clock Input.
Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CLK
CE
1
CE
2
CE
3
OE
Input-
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE
2
and CE
3
to select/deselect the device.
Input-
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE
1
and CE
3
to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE
1
and CE
2
to select/deselect the device.
Input-
Output Enable, active LOW.
Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected
state and when the device has been deselected.
Input-
Clock Enable Input, active LOW.
When asserted LOW the clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
I/O-
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
[17:0]
during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQ
a
–DQ
d
are placed in a tri-state condition. The outputs are automat-
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
I/O-
Bidirectional Data Parity I/O lines.
Functionally, these signals are identical to DQ
s
. During write
Synchronous sequences, DQP
a
is controlled by BW
a
, DQP
b
is controlled by BW
b
, DQP
c
is controlled by BW
c
,
and DQP
d
is controlled by BW
d
.
Input Strap Pin
Mode Input.
Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
JTAG serial
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK.
output
Synchronous
JTAG serial
Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK.
input
Synchronous
Test Mode
This pin controls the Test Access Port state machine.
Sampled on the rising edge of TCK.
Select
Synchronous
JTAG-Clock
Clock input to the JTAG circuitry.
Power Supply
Power supply inputs to the core of the device.
Page 6 of 28
CEN
DQ
S
DQP
X
MODE
TDO
TDI
TMS
TCK
V
DD
Document #: 38-05555 Rev. *F