CY7C1061AV33-10ZXC Datasheet Download

Part No.:
CY7C1061AV33-10ZXC
Download:
Download Datasheet
Description:
[16-Mbit (1 M × 16) Static RAM]
File Size:
417 K
Page:
13 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C1061AV33
DC Input Voltage
............................. –0.5 V to V
CC
+ 0.5 V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65
°C
to +150
°C
Ambient Temperature with
Power Applied .......................................... –55
°C
to +125
°C
Supply Voltage on V
CC
to Relative GND
..–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High-Z State
................................. –0.5 V to V
CC
+ 0.5 V
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°C
to +70
°C
–40
°C
to +85
°C
V
CC
3.3 V
±
0.3 V
DC Electrical Characteristics
(Over the Operating Range)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= max,
f = f
max
= 1/t
RC
Commercial
Industrial
Test Conditions
I
OH
= –4.0 mA
I
OL
= 8.0 mA
2.0
–0.3
–1
–1
–10
Min
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
275
275
70
Max
Unit
V
V
V
V
μA
μA
mA
mA
mA
CE
2
<= V
IL,
max V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
max
CE
2
<= 0.3 V
max V
CC
,
CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V,
or V
IN
< 0.3 V, f = 0
Commercial/
Industrial
50
mA
Capacitance
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25
°C,
f = 1 MHz, V
CC
= 3.3 V
TSOP II
6
8
FBGA
8
10
Unit
pF
pF
AC Test Loads and Waveforms
50Ω
OUTPUT
Z
0
= 50Ω
V
TH
= 1.5 V
30 pF* * Capacitive Load consists of all
components of the test environment.
3.3 V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(b)
R2
351Ω
R1 317
Ω
(a)
ALL INPUT PULSES
3.3 V
90%
GND
Rise time > 1 V/ns
10%
90%
10%
Fall time:
> 1 V/ns
(c)
Notes
3. V
IL
(min) = –2.0 V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0 V). As soon as 1 ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0 V) voltage.
Document #: 38-05256 Rev. *J
Page 4 of 13