CY7C1061AV33-10ZXC Datasheet Download

Part No.:
CY7C1061AV33-10ZXC
Download:
Download Datasheet
Description:
[16-Mbit (1 M × 16) Static RAM]
File Size:
417 K
Page:
13 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C1061AV33-10ZXC Datasheet Page:2CY7C1061AV33-10ZXC Datasheet Page:3CY7C1061AV33-10ZXC Datasheet Page:4CY7C1061AV33-10ZXC Datasheet Page:5CY7C1061AV33-10ZXC Datasheet Page:6CY7C1061AV33-10ZXC Datasheet Page:7CY7C1061AV33-10ZXC Datasheet Page:8CY7C1061AV33-10ZXC Datasheet Page:9 
CY7C1061AV33
16-Mbit (1 M × 16) Static RAM
Features
Functional Description
The CY7C1061AV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE
1
LOW and CE
2
HIGH)
while forcing the Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
),
is written into the location specified on the address pins (A
0
through A
19
). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O
8
through I/O
15
) is written into the location specified
on the address pins (A
0
through A
19
).
To read from the device, enable the chip by taking CE
1
LOW and
CE
2
HIGH while forcing the Output Enable (OE) LOW and the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins will
appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O
8
to I/O
15
. See
for a complete description of Read and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH/CE
2
LOW), the outputs are disabled (OE HIGH), the BHE
and BLE are disabled (BHE, BLE HIGH), or a Write operation is
in progress (CE
1
LOW, CE
2
HIGH, and WE LOW).
High speed
t
AA
= 10 ns
Low active power
990 mW (max)
Operating voltages of 3.3 ± 0.3 V
2.0 V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE
1
and CE
2
features
Available in Pb-free and non Pb-free 54-pin TSOP II package
and non Pb-free 60-ball fine pitch ball grid array (FBGA)
package
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
SENSE AMPS
1M x 16
ARRAY
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN
DECODER
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
BHE
WE
OE
BLE
CE
2
CE
1
Cypress Semiconductor Corporation
Document #: 38-05256 Rev. *J
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised February 2, 2011