CY7C199-20PC Datasheet Download

Part No.:
CY7C199-20PC
Download:
Download Datasheet
Description:
[32K x 8 Static RAM]
File Size:
319 K
Page:
13 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C199
Switching Characteristics
Over the Operating Range (-8, -10, -12, -15)
7C199-8
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
CE LOW to
CE HIGH to
[8, 9]
[3, 7]
7C199-10
Min.
10
Max.
7C199-12
Min.
12
Max.
7C199-15
Min.
15
Max.
Unit
ns
15
3
15
7
0
7
3
7
0
15
15
10
10
0
0
9
9
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
3
ns
ns
Description
Min.
8
Max.
8
3
8
4.5
0
5
3
4
0
8
8
7
7
0
0
7
5
0
5
3
3
10
7
7
0
0
7
5
0
0
3
0
3
10
3
10
5
0
5
3
5
0
10
12
9
9
0
0
8
8
0
6
3
12
12
5
5
5
12
Low-Z
[8]
High-Z
[8,9]
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[9]
WE HIGH to
Low-Z
[8]
Write Cycle
[10, 11]
7
Switching Characteristics
Over the Operating Range (-20, -25, -35, -45)
[3, 7]
7C199-20
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[8]
CE HIGH to
High-Z
[8, 9]
0
CE LOW to Power-up
3
9
0
0
9
3
11
0
3
20
9
0
11
3
15
0
20
20
3
25
10
0
15
3
15
25
25
3
35
16
0
15
35
35
3
45
16
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C199-25
Min.
Max.
7C199-35
Min.
Max.
7C199-45
Min.
Max.
Unit
Shaded area contains advance information.
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05160 Rev. *A
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