CY7C199-12VC Datasheet Download

Part No.:
CY7C199-12VC
Download:
Download Datasheet
Description:
[32K x 8 Static RAM]
File Size:
315 K
Page:
16 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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99
CY7C199
32K x 8 Static RAM
Features
• High speed
— 10 ns
• Fast t
DOE
• CMOS for optimum speed/power
• Low active power
— 467 mW (max, 12 ns “L” version)
• Low standby power
— 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
provided by an active LOW Chip Enable (CE) and active LOW
Output Enable (OE) and three-state drivers. This device has
an automatic power-down feature, reducing the power con-
sumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Functional Description
The CY7C199 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP / SOJ / SOIC
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22
23
24
25
26
27
28
1
2
3
4
5
6
7
LCC
Top View
3 2 1 28 27
4
26 A
4
5
25 A
3
6
24 A
2
7
23 A
1
8
22 OE
9
21 A
0
20 CE
10
11
19 I/O
7
12
18 I/O
6
1314151617
C199–3
I/O2
GND
I/O3
I/O4
I/O5
A7
A6
A5
VCC
WE
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
C199–2
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
CE
WE
OE
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
1024 x 32 x 8
ARRAY
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
3
I/O
4
I/O
5
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
TSOP I
Top View
(not to scale)
A
10
A
12
A
13
A
11
A
14
C199–1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
C199–4
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)
L
Maximum CMOS
Standby Current (mA) L
7C199-8
8
120
0.5
7C199-10 7C199-12
10
12
110
160
90
90
0.5
10
0.05
0.05
7C199-15 7C199-20
15
20
155
150
90
90
10
10
0.05
0.05
7C199-25 7C199-35
25
35
150
140
80
70
10
10
0.05
0.05
7C199-45
45
140
10
Shaded area contains advance information.
Cypress Semiconductor Corporation
Document #: 38-05160 Rev. **
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised September 7, 2001