CY7C188-15VC Datasheet Download

Part No.:
CY7C188-15VC
Download:
Download Datasheet
Description:
[32K x 9 Static RAM]
File Size:
245 K
Page:
7 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C188
32K x 9 Static RAM
Features
• High speed
— 15 ns
• Automatic power-down when deselected
• Low active power
— 660 mW
• Low standby power
— 55 mW
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
1
, CE
2
, and OE
features
• Available in non Pb-free 32-Lead (300-Mil) Molded SOJ
Functional Description
The CY7C188 is a high-performance CMOS static RAM
organized as 32,768 words by 9 bits. Easy memory expansion
is provided by an active-LOW chip enable (CE
1
), an
active-HIGH chip enable (CE
2
), an active-LOW output enable
(OE), and tri-state drivers. The device has an automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking CE
1
and write
enable (WE) inputs LOW and CE
2
input HIGH. Data on the
nine I/O pins (I/O
o
– I/O
8
) is then written into the location
specified on the address pins (A
0
– A
14
).
Reading from the device is accomplished by taking CE
1
and
OE LOW while forcing WE and CE
2
HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The nine input/output pins (I/O
0
– I/O
8
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C188 is available in standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
NC
NC
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
I/O
3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
14
CE
2
WE
A
13
A
9
A
10
A
11
OE
A
12
CE
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
C188–2
I/O
0
INPUT BUFFER
I/O
1
I/O
2
SENSE AMPS
A
0
A
1
A
2
A
3
A
4
A
5
A
6
ROW DECODER
I/O
3
I/O
4
I/O
5
I/O
6
32K x 9
ARRAY
CE
1
CE
2
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
7
I/O
8
C188–1
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
Cypress Semiconductor Corporation
Document #: 38-05053 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 28, 2006