CY7C185-25PC Datasheet Download

Part No.:
CY7C185-25PC
Download:
Download Datasheet
Description:
[8K x 8 Static RAM]
File Size:
200 K
Page:
11 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C185-25PC Datasheet Page:2CY7C185-25PC Datasheet Page:3CY7C185-25PC Datasheet Page:4CY7C185-25PC Datasheet Page:5CY7C185-25PC Datasheet Page:6CY7C185-25PC Datasheet Page:7CY7C185-25PC Datasheet Page:8CY7C185-25PC Datasheet Page:9 
185
CY7C185
8K x 8 Static RAM
Features
• High speed
— 15 ns
• Fast t
DOE
• Low active power
— 715 mW
• Low standby power
— 220 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE
1
, CE
2
, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), and active LOW output enable (OE) and
three-state drivers. This device has an automatic power-down
feature (CE
1
or CE
2
), reducing the power consumption by 70%
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
1
and WE in-
puts are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address
pins (A
0
through A
12
). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Functional Description
The CY7C185 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
C185–2
I/O
0
INPUT BUFFER
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
CE
1
CE
2
WE
OE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
256 x 32 x 8
ARRAY
COLUMN DECODER
POWER
DOWN
SENSE AMPS
I/O
7
A
10
A
11
A
12
A
0
A
9
C185–1
Selection Guide
[1]
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Note:
1. For military specifications, see the CY7C185A data sheet.
7C185–15
15
130
40/15
7C185–20
20
110
20/15
7C185–25
25
100
20/15
7C185–35
35
100
20/15
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. **
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised August 24, 2001