CY7C185-20VC Datasheet Download

Part No.:
CY7C185-20VC
Download:
Download Datasheet
Description:
[8K x 8 Static RAM]
File Size:
306 K
Page:
12 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C185
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1 481
5V
OUTPUT
5 pF
INCLUDING
JIGAND
SCOPE
R1 481
3.0V
R2
255Ω
GND
10%
ALL INPUT PULSES
90%
90%
10%
5 ns
R2
255Ω
5 ns
Equivalent to:
OUTPUT
(a)
(b)
THÉVENIN EQUIVALENT
167Ω
1.73V
Switching Characteristics
Over the Operating Range
[4]
-15
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
t
PU
t
PD
Write Cycle
[7]
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW to Write End
CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[5]
WE HIGH to Low Z
3
15
12
12
12
0
0
12
8
0
7
5
20
15
15
15
0
0
15
10
0
7
5
25
20
20
20
0
0
15
10
0
7
5
35
20
20
25
0
0
20
12
0
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid
CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5]
CE
1
LOW to Low Z
[6]
CE
2
HIGH to Low Z
CE
1
HIGH to High Z
[5, 6]
CE
2
LOW to High Z
CE
1
LOW to Power-Up
CE
2
to HIGH to Power-Up
CE
1
HIGH to Power-Down
CE
2
LOW to Power-Down
0
15
3
3
7
0
20
3
7
5
3
8
0
20
3
15
15
8
3
8
5
3
10
0
20
15
15
5
20
20
9
3
10
5
3
10
20
20
5
25
25
12
3
10
25
25
5
35
35
15
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-20
Max.
Min.
-25
Max.
Min.
-35
Max.
Unit
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE,
t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE1
and t
LZCE2
for any given device.
7. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *B
Page 3 of 12