CY7C1399B-15ZC Datasheet Download

Part No.:
CY7C1399B-15ZC
Download:
Download Datasheet
Description:
[32K x 8 3.3V Static RAM]
File Size:
153 K
Page:
10 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C1399B-15ZC Datasheet Page:2CY7C1399B-15ZC Datasheet Page:3CY7C1399B-15ZC Datasheet Page:4CY7C1399B-15ZC Datasheet Page:5CY7C1399B-15ZC Datasheet Page:6CY7C1399B-15ZC Datasheet Page:7CY7C1399B-15ZC Datasheet Page:8CY7C1399B-15ZC Datasheet Page:9 
C1399B
CY7C1399B
32K x 8 3.3V Static RAM
Features
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
— 10/12/15 ns
• Low active power
— 216 mW (max.)
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
active LOW Output Enable (OE) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399B is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
Functional Description
[1]
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
INPUT BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
CE
WE
OE
ROW DECODER
I/O
2
SENSE AMPS
32K x 8
ARRAY
I/O
3
I/O
4
I/O
5
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
10
A
11
A
12
A
13
Selection Guide
1399B-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (µA)
L
10
60
500
50
1399B-12
12
55
500
50
1399B-15
15
50
500
50
1399B-20
20
45
500
50
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05071 Rev. *C
A
14
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised June 19, 2001