CY7C1370D-167AXI Datasheet Download

Part No.:
CY7C1370D-167AXI
Download:
Download Datasheet
Description:
[18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL⑩ Architecture]
File Size:
462 K
Page:
28 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C1370D-167AXI Datasheet Page:2CY7C1370D-167AXI Datasheet Page:3CY7C1370D-167AXI Datasheet Page:4CY7C1370D-167AXI Datasheet Page:5CY7C1370D-167AXI Datasheet Page:6CY7C1370D-167AXI Datasheet Page:7CY7C1370D-167AXI Datasheet Page:8CY7C1370D-167AXI Datasheet Page:9 
CY7C1370D
CY7C1372D
18-Mbit (512K x 36/1M x 18) Pipelined
SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 3.3V core power supply (V
DD
)
• 3.3V/2.5V I/O power supply(V
DDQ
)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and
1M x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1370D and CY7C1372D are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1370D and CY7C1372D are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
–BW
d
for CY7C1370D and BW
a
–BW
b
for CY7C1372D)
and a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1370D (512K x 36)
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
a
DQP
b
DQP
c
DQP
d
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Cypress Semiconductor Corporation
Document #: 38-05555 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 28, 2006