Address Strobe from Controller, sampled
on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A[1:0] are also loaded into the
burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
Byte Write Enable Input, active LOW.
Synchronous Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
ZZ “sleep” Input, active HIGH.
Asynchronous asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
Bidirectional Data I/O lines.
As inputs, they
Synchronous feed into an on-chip data register that is
triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQ
in a three-state condition.The outputs are
automatically three-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
51,80,1,30 P6,D6,D2, N11,C11,C1,
Bidirectional Data Parity I/O Lines.
Synchronous Functionally, these signals are identical to
. During write sequences, DQP
controlled by BW
Selects Burst Order.
When tied to GND
selects linear burst sequence. When tied to
or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
15,41,65,91 15,41,65,91 J2,C4,J4,
Power supply inputs to the core of the
4,11,20,27, 4,11,20,27, A1,F1,J1,
54,61,70,77 54,61,70,77 M1,U1,
Power supply for the I/O circuitry.
Document #: 38-05302 Rev. *B
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