CY7C1360B-166AC Datasheet Download

Part No.:
CY7C1360B-166AC
Download:
Download Datasheet
Description:
[9-Mbit (256K x 36/512K x 18) Pipelined SRAM]
File Size:
859 K
Page:
34 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C1360B
CY7C1362B
CY7C1360B–Pin Definitions
Name
A
0
, A
1
, A
TQFP
3-Chip
Enable
37,36,32,
33,34,35,
43,44,45,
46,47,48,
49,50,81,
82,99,100
TQFP
2-Chip
Enable
BGA
fBGA
I/O
Description
Input-
Address Inputs used to select one of the 256K
P4,N4, R6,P6,A2,
37,36,32,
A10,B2, Synchronous
address locations.
Sampled at the rising edge of
A2,C2,
33,34,35,
the CLK if ADSP or ADSC is active LOW, and CE
1
,
R2,3A, B10,P3,P4,
44,45,46,
B3,C3, P8,P9,P10,
47,48,49,
CE
2
, and CE
3[2]
are sampled active. A
1
, A
0
are fed
50,81,82, T3,T4,A5, P11,R3,R4,
to the two-bit counter..
92,99,100 B5,C5, R8,R9,R10,
R11
T5,A6,B6,
C6,R6
93,94,95,
96
88
L5,G5,
G3,L3
H4
B5,A5,A4,
B4
B7
Input-
Byte Write Select Inputs, active LOW.
Qualified
Synchronous with BWE to conduct Byte Writes to the SRAM.
Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW.
When
Synchronous asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written,
regardless of the values on BW
X
and BWE).
Input-
Byte Write Enable Input, active LOW.
Sampled
Synchronous on the rising edge of CLK. This signal must be as-
serted LOW to conduct a Byte Write.
Input-
Clock
Clock Input.
Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a
burst operation.
BW
A,
BW
B
BW
C,
BW
D
GW
93,94,95,
96
88
BWE
87
87
M4
A7
CLK
89
89
K4
B6
CE
1
98
98
E4
A3
Input-
Chip Enable 1 Input, active LOW.
Sampled on the
Synchronous rising edge of CLK. Used in conjunction with CE
2
and CE
3[2]
to select/deselect the device. ADSP is
ignored if CE
1
is HIGH.
Input-
Chip Enable 2 Input, active HIGH.
Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE
1
and CE
3[2]
to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW.
Sampled on the
Synchronous rising edge of CLK. Used in conjunction with CE
1
and CE
2
to select/deselect the device. Not available
for AJ package version. Not connected for BGA.
Where referenced, CE
3[2]
is assumed active
throughout this document for BGA.
Input-
Asynchro-
nous
Output Enable, asynchronous input, active
LOW.
Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the first
clock of a read cycle when emerging from a
deselected state.
CE
2
97
97
B2
B3
CE
3[2]
92
-
-
A6
OE
86
86
F4
B8
ADV
83
83
G4
A9
Input-
Advance Input signal, sampled on the rising
Synchronous
edge of CLK, active LOW.
When asserted, it
automatically increments the address in a burst
cycle.
Document #: 38-05291 Rev. *C
Page 6 of 34