CY7C1354B-166AC Datasheet Download

Part No.:
CY7C1354B-166AC
Download:
Download Datasheet
Description:
[9-Mb (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture]
File Size:
475 K
Page:
29 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C1354B
CY7C1356B
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1354B and CY7C1356B are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ
and DQP
(DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1354B and DQ
a,b
/DQP
a,b
for
CY7C1356B) inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ
and DQP
(DQ
a,b,c,d
/
DQP
a,b,c,d
for CY7C1354B and DQ
a,b
/DQP
a,b
for
CY7C1356B) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1354B/56B has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
1
, CE
2
, and CE
3
) and WE inputs are
ignored and the burst counter is incremented. The correct BW
(BW
a,b,c,d
for CY7C1354B and BW
a,b
for CY7C1356B) inputs
must be driven in each cycle of the burst write in order to write
the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3,
must remain inactive for
the duration of t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
00
11
10
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
10
11
00
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ
>
V
DD
0.2V
ZZ
>
V
DD
0.2V
ZZ
<
0.2V
This parameter is sampled
This parameter is sampled
Min.
Max
35
2t
CYC
2t
CYC
0
Unit
mA
ns
ns
ns
ns
2t
CYC
Document #: 38-05114 Rev. *C
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