CY7C1325B-100AC Datasheet Download

Part No.:
CY7C1325B-100AC
Download:
Download Datasheet
Description:
[256K x 18 Synchronous 3.3V Cache RAM]
File Size:
340 K
Page:
17 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C1325B-100AC Datasheet Page:2CY7C1325B-100AC Datasheet Page:3CY7C1325B-100AC Datasheet Page:4CY7C1325B-100AC Datasheet Page:5CY7C1325B-100AC Datasheet Page:6CY7C1325B-100AC Datasheet Page:7CY7C1325B-100AC Datasheet Page:8CY7C1325B-100AC Datasheet Page:9 
CY7C1325B
256K x 18 Synchronous
3.3V Cache RAM
Features
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 256K by 18 common I/O
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
• Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequence
• Separate processor and controller address strobes pro-
vide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• I/Os capable of 2.5–3.3V operation
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
Functional Description
The CY7C1325B is a 3.3V, 256K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1325B allows both interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the Cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A
[17:0]
GW
BWE
BW
1
MODE
(A
0
,A
1
) 2
BURST Q
0
CE COUNTER
Q
1
CLR
Q
ADDRESS
CE REGISTER
D
16
18
18
16
256K X 18
MEMORY
ARRAY
D
Q
DQ[15:8]
BYTEWRITE
REGISTERS
Q
DQ[7:0]
BYTEWRITE
REGISTERS
D
BW
0
CE
1
CE
2
CE
3
D
ENABLE Q
CE REGISTER
CLK
18
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[15:0]
DP
[1:0]
Selection Guide
7C1325B-117
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Intel and Pentium are registered trademarks of Intel Corporation.
7C1325B-100
8.0
325
10.0
7.5
350
10.0
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
September 7, 2000