CY7C131-35JI Datasheet Download

Part No.:
CY7C131-35JI
Download:
Download Datasheet
Description:
[1K x 8 Dual-Port Static RAM]
File Size:
573 K
Page:
19 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics
Over the Operating Range
7C131-15
7C141-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
7C130-25
7C131-25
7C140-25
7C141-25
Min.
25
Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
30
Max.
Unit
ns
30
0
30
20
3
15
5
15
0
25
30
25
25
2
0
25
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
0
ns
ns
Description
Min.
15
Max.
15
0
15
10
3
10
3
10
0
15
15
12
12
2
0
12
10
0
10
0
0
25
20
20
2
0
15
15
0
0
5
3
0
25
25
15
15
15
25
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
WRITE CYCLE
15
Shaded areas contain preliminary information.
Note:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL
/I
OH,
and 30-pF load capacitance.
12. AC Test Conditions use V
OH
= 1.6V and V
OL
= 1.4V.
13. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
14. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE
, t
HZCE
and t
HZWE
are tested with C
L
= 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-06002 Rev. *D
Page 5 of 19