CY7C128A-35PC Datasheet Download

Part No.:
CY7C128A-35PC
Download:
Download Datasheet
Description:
[2K x 8 Static RAM]
File Size:
205 K
Page:
11 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C128A
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
255
R1 481
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
255
R1 481
ALL INPUT PULSES
3.0V
GND
10%
90%
90%
10%
5 ns
5 ns
(a)
(b)
C128A–4
C128A–5
THÉVENIN EQUIVALENT
167
1.73V
OUTPUT
Switching Characteristics
Over the Operating Range
[2, 6]
7C128A-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[7]
CE LOW to Low Z
[8]
CE HIGH to High Z
[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
[9]
7C128A-20
Min.
20
Max.
7C128A-25
Min.
25
Max.
7C128A-35
Min.
35
Max.
7C128A-45
Min.
45
Max.
Unit
ns
45
5
45
20
3
15
5
15
0
25
40
30
30
0
0
20
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
5
ns
ns
Description
Min.
15
Max.
15
5
15
10
3
8
5
8
0
15
15
12
12
0
0
12
10
0
7
5
5
20
15
15
0
0
15
10
0
0
5
3
5
20
5
20
10
3
8
5
8
0
20
20
20
20
0
0
15
10
0
7
5
25
5
25
12
3
10
5
10
0
20
25
25
25
0
0
20
15
0
7
5
35
35
15
12
15
20
WRITE CYCLE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[7]
WE HIGH to Low Z
10
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05028 Rev. **
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