CY7C128A-35PC Datasheet Download

Part No.:
CY7C128A-35PC
Download:
Download Datasheet
Description:
[2K x 8 Static RAM]
File Size:
205 K
Page:
11 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C128A-35PC Datasheet Page:2CY7C128A-35PC Datasheet Page:3CY7C128A-35PC Datasheet Page:4CY7C128A-35PC Datasheet Page:5CY7C128A-35PC Datasheet Page:6CY7C128A-35PC Datasheet Page:7CY7C128A-35PC Datasheet Page:8CY7C128A-35PC Datasheet Page:9 
28A
CY7C128A
2K x 8 Static RAM
Features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
— 15 ns
• Low active power
— 660 mW (commercial)
— 688 mW (military—20 ns)
• Low standby power
— 110 mW (20 ns)
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electro-
static discharge
• V
IH
of 2.2V
provided by an active LOW Chip Enable (CE), and active LOW
Output Enable (OE) and three-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O
0
through I/O
7
) is written into the
memory location specified on the address pins (A
0
through
A
10
).
Reading the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while Write Enable (WE)
remains HIGH. Under these conditions, the contents of the
memory location specified on the address pins will appear on
the eight I/O pins.
The I/O pins remain in high-impedance state when Chip En-
able (CE) or Output Enable (OE) is HIGH or Write Enable (WE)
is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
Functional Description
The CY7C128A is a high-performance CMOS static RAM or-
ganized as 2048 words by 8 bits. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
24
23
2
22
3
4
21
5
20
6
19
7C128A
18
7
17
8
9
16
10
15
11
14
12
13
V
CC
A
8
A
9
WE
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
C128A–2
INPUT BUFFER
I/O
0
I/O
1
ROW DECODER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
CE
WE
OE
I/O
2
SENSE AMPS
128 x 16 x 8
ARRAY
I/O
3
I/O
4
I/O
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
LCC
Top View
A5
A6
A7
VCC
A8
3 2 1 24 23
4
22
5
21
6
20
7 7C128A 19
8
18
9
17
10
16
11 12 13 14 15
I/O 2
GND
I/O 3
I/O 4
I/O 5
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
9
WE
OE
A
10
CE
I/O
7
I/O
6
C128A–3
A
3
A
2
A
1
A
0
C128A–1
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Commercial
Current (mA)
Military
Maximum Standby
Commercial
Current (mA)
Military
7C128A-15
15
120
-
40
-
7C128A-20
20
120
125
20
20
7C128A-25
25
120
125
20
20
7C128A-35
35
120
125
20
20
7C128A-45
45
120
125
20
20
Cypress Semiconductor Corporation
Document #: 38-05028 Rev. **
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised August 24, 2001