CY7C1069AV33-10ZXC Datasheet Download

Part No.:
CY7C1069AV33-10ZXC
Download:
Download Datasheet
Description:
[2M x 8 Static RAM]
File Size:
396 K
Page:
9 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C1069AV33-10ZXC Datasheet Page:2CY7C1069AV33-10ZXC Datasheet Page:3CY7C1069AV33-10ZXC Datasheet Page:4CY7C1069AV33-10ZXC Datasheet Page:5CY7C1069AV33-10ZXC Datasheet Page:6CY7C1069AV33-10ZXC Datasheet Page:7CY7C1069AV33-10ZXC Datasheet Page:8CY7C1069AV33-10ZXC Datasheet Page:9 
CY7C1069AV33
2M x 8 Static RAM
Features
• High speed
— t
AA
= 10, 12 ns
• Low active power
— 990 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
1
and CE
2
features
• Available in Pb-free and non Pb-free 54-pin TSOP II ,
non Pb-free 60-ball fine-pitch ball grid array (FBGA)
package
Functional Description
The CY7C1069AV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE
1
LOW and CE
2
HIGH) as well as forcing the Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a Write operation (CE
1
LOW, CE
2
HIGH, and WE
LOW).
The CY7C1069AV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
60-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
Pin Configurations
[1, 2]
TSOP II
Top View
NC
V
CC
NC
I/O
6
V
SS
I/O
7
A
4
A
3
A
2
A
1
A
0
NC
CE
1
V
CC
WE
CE
2
A
19
A
18
A
17
A
16
A
15
I/O
0
V
CC
I/O
1
NC
V
SS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Data in Drivers
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
CE
1
CE
2
WE
OE
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
2048K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
NC
V
SS
NC
I/O
5
V
CC
I/O
4
A
5
A
6
A
7
A
8
A
9
NC
OE
V
SS
DNU
A
20
A
10
A
11
A
12
A
13
A
14
I/O
3
V
SS
I/O
2
NC
ROW DECODER
V
CC
NC
A
17
A
18
A
19
A
20
A
16
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document #: 38-05255 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 3, 2006