CY7C1061AV33-10ZXC Datasheet Download

Part No.:
CY7C1061AV33-10ZXC
Download:
Download Datasheet
Description:
[16-Mbit (1M x 16) Static RAM]
File Size:
642 K
Page:
10 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C1061AV33-10ZXC Datasheet Page:1CY7C1061AV33-10ZXC Datasheet Page:2CY7C1061AV33-10ZXC Datasheet Page:3CY7C1061AV33-10ZXC Datasheet Page:5CY7C1061AV33-10ZXC Datasheet Page:6CY7C1061AV33-10ZXC Datasheet Page:7CY7C1061AV33-10ZXC Datasheet Page:8CY7C1061AV33-10ZXC Datasheet Page:9 
CY7C1061AV33
AC Switching Characteristics
(Over the Operating Range)
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE
1
LOW/CE
2
HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low-Z
Description
–10
Min
1
10
10
3
10
5
1
5
3
5
0
10
5
1
5
10
7
7
0
0
7
5.5
0
3
5
7
8
12
8
8
0
0
8
6
0
3
1
0
3
1
3
Max
Min
1
12
–12
Max
Unit
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW/CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE
1
LOW/CE
2
HIGH to Low-Z
CE
1
HIGH/CE
2
LOW to High-Z
CE
1
LOW/CE
2
HIGH to Power Up
CE
1
HIGH/CE
2
LOW to Power Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
ms
ns
12
12
6
6
6
12
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
ns
ns
WE LOW to High-Z
Byte Enable to End of Write
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the
unless specified otherwise.
7. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. t
power
time must be provided initially before a Read/Write operation is started.
8. t
HZOE
, t
HZCE
, t
HZWE
, t
HZBE
and t
LZOE
, t
LZCE
, t
\LZWE
, t
LZBE
are specified with a load capacitance of 5 pF as in (b) of
Transition is measured
±200
mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE
1
LOW (CE
2
HIGH) and WE LOW. Chip enables must be active and WE and byte enables
must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to
the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05256 Rev. *G
Page 4 of 10