CY7C1041CV33-10ZC Datasheet Download

Part No.:
CY7C1041CV33-10ZC
Download:
Download Datasheet
Description:
[256K x 16 Static RAM]
File Size:
229 K
Page:
11 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C1041CV33
AC Switching Characteristics
[4]
Over the Operating Range
-8
Parameter
Read Cycle
t
power[5]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[6, 7]
CE LOW to Low-Z
[7]
CE HIGH to High-Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[7]
WE LOW to
High-Z
[6, 7]
6
Byte Enable to End of Write
8
6
6
0
0
6
4
0
3
4
7
0
6
10
7
7
0
0
7
5
0
3
5
8
0
8
4
0
6
12
8
8
0
0
8
6
0
3
6
10
3
4
0
10
5
0
6
15
10
10
0
0
10
7
0
3
7
10
0
4
3
5
0
12
6
0
7
20
10
10
0
0
10
8
0
3
8
3
8
4
0
5
3
6
0
15
7
0
8
1
8
8
3
10
5
0
6
3
7
0
20
8
1
10
10
3
12
6
0
7
3
8
1
12
12
3
15
7
0
8
1
15
15
3
20
8
1
20
20
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
-10
Max.
-12
Min.
Max.
-15
Min.
Max.
-20
Min.
Max.
Unit
Min. Max. Min.
Write Cycle
[8, 9]
Shaded areas contain advance information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05134 Rev. *D
Page 4 of 11