CY7C1041CV33-10ZXC Datasheet Download

Part No.:
CY7C1041CV33-10ZXC
Download:
Download Datasheet
Description:
[4-Mbit (256K x 16) Static RAM]
File Size:
599 K
Page:
12 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C1041CV33
4-Mbit (256K x 16) Static RAM
Features
• Pin equivalent to CY7C1041BV33
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• High speed
— t
AA
= 10 ns
• Low active power
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free and non Pb-free 44-pin 400-mil-
SOJ, 44-pin TSOP II and 48-ball FBGA packages
Functional Description
[1]
The CY7C1041CV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable
(BLE) is LOW, then data from I/O pins (I/O
0
–I/O
7
), is written
into the location specified on the address pins (A
0
–A
17
). If Byte
HIGH Enable (BHE) is LOW, then data from I/O pins
(I/O
8
–I/O
15
) is written into the location specified on the
address pins (A
0
–A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
– I/O
7
. If Byte HIGH Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
0
–I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1041CV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
INPUT BUFFER
Pin Configuration
SOJ/
TSOP II
Top View
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
256K × 16
ARRAY
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN
DECODER
BHE
WE
CE
OE
BLE
A
17
A
16
A
15
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
14
A
13
A
12
A
11
A
10
ROW DECODER
Notes:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 38-05134 Rev. *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 1, 2006