CY7C1041B-15ZI Datasheet Download

Part No.:
CY7C1041B-15ZI
Download:
Download Datasheet
Description:
[256K x 16 Static RAM]
File Size:
344 K
Page:
10 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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1CY7C1041B
CY7C1041B
256K x 16 Static RAM
Features
• High speed
t
AA
= 12 ns
• Low active power
1540 mW (max.)
• Low CMOS standby power (L version)
2.75 mW (max.)
• 2.0V Data Retention (400
µW
at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
8
to I/O
15
. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041B is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Functional Description
The CY7C1041B is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
Logic Block Diagram
INPUT BUFFER
Pin Configuration
SOJ
TSOP II
Top View
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
256K x 16
ARRAY
1024 x 4096
I/O
0
– I/O
7
I/O
8
– I/O
15
COLUMN
DECODER
BHE
WE
CE
OE
BLE
1041B–1
A
17
A
16
A
15
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
14
A
13
A
12
A
11
A
10
1041B–2
ROW DECODER
Selection Guide
7C1041B-12
Maximum Access Time (ns)
Maximum Operating Current (mA) Com’l
Ind’l
Maximum CMOS Standby Current Com’l
(mA)
Com’l
Ind’l
L
12
200
220
3
-
-
7C1041B-15
15
190
210
3
0.5
6
7C1041B-17
17
180
200
3
0.5
6
7C1041B-20
20
170
190
3
0.5
6
7C1041B-25
25
160
180
3
0.5
6
Cypress Semiconductor Corporation
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
SENSE AMPS
3901 North First Street
San Jose
CA 95134
408-943-2600
March 23, 2001