CY7C1032-10JC Datasheet Download

Part No.:
CY7C1032-10JC
Download:
Download Datasheet
Description:
[64K x 18 Synchronous Cache RAM]
File Size:
283 K
Page:
13 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C1031
CY7C1032
64K x 18 Synchronous Cache RAM
Features
• Supports 66-MHz Pentium
®
microprocessor cache
systems with zero wait states
• 64K by 18 common I/O
• Fast clock-to-output times
— 8.5 ns
• Two-bit wraparound counter supporting Pentium
microprocessor and 486 burst sequence (CY7C1031)
• Two-bit wraparound counter supporting linear burst
sequence (CY7C1032)
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interface with the processor and external cache
controller
• Asynchronous output enable
• I/Os capable of 3.3V operation
• JEDEC-standard pinout
• 52-pin PLCC packaging
Functional Description
The CY7C1031 and CY7C1032 are 64K by 18 synchronous
cache RAMs designed to interface with high-speed micropro-
cessors with minimum glue logic. Maximum access delay from
clock rise is 8.5 ns. A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access.
The CY7C1031 is designed for Intel
®
Pentium and i486
CPU-based systems; its counter follows the burst sequence of
the Pentium and the i486 processors. The CY7C1032 is archi-
tected for processors with linear burst sequences. Burst
accesses can be initiated with the processor address strobe
(ADSP) or the cache controller address strobe (ADSC) inputs.
Address advancement is controlled by the address
advancement (ADV) input.
A synchronous self-timed write mechanism is provided to
simplify the write interface. A synchronous chip select input
and an asynchronous output enable input provide easy control
for bank selection and output three-state control.
Logic Block Diagram
18
DATA
IN
REGISTER
ADDR
REG
9
14
2
ADV
LOGIC
16
9
DQ
8
DQ
9
V
CCQ
V
SSQ
DQ
10
DQ
11
DQ
12
DQ
13
V
SSQ
V
CCQ
DQ
14
DQ
15
[1]
DP
1
Pin Configuration
PLCC
Top View
WH
WL
ADSC
ADSP
ADV
CLK
OE
A8
A9
A10
16
A
15
–A
0
14
2
ADV
64K X 9
64K X 9
RAM ARRAY RAM ARRAY
CLK
ADSP
ADSC
CS
WH
WL
TIMING
CONTROL
WH
WL
9
9
8
9
10
11
12
13
14
15
16
17
18
19
20
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C1031
7C1032
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
CS
A6
A7
DP
0
DQ
7
DQ
6
[1]
V
CCQ
V
SSQ
DQ
5
DQ
4
DQ
3
DQ
2
V
SSQ
V
CCQ
DQ
1
DQ
0
18
DQ
15
– DQ
0
DP
1
– DP
0
OE
Selection Guide
7C1031-8
7C1032-8
Maximum Access Time
Maximum Operating Current
Commercial
Note:
1. DP
0
and DP
1
are functionally equivalent to DQ
x
.
7C1031-10
7C1032-10
10
280
A5
A
4
A
3
A
2
A1
A0
GND
V CC
A
15
A14
A13
A12
A11
7C1031-12
12
230
Unit
ns
mA
8.5
280
Cypress Semiconductor Corporation
Document #: 38-05278 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 1, 2004