CY7C1021B-15ZC Datasheet Download

Part No.:
CY7C1021B-15ZC
Download:
Download Datasheet
Description:
[1-Mbit (64K x 16) Static RAM]
File Size:
320 K
Page:
10 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C1021B
1-Mbit (64K x 16) Static RAM
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• High speed
— t
AA
= 12 ns (Commercial & Industrial)
— t
AA
= 15 ns (Automotive)
• CMOS for optimum speed/power
• Low active power
— 770 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in Pb-free and non Pb-free 44-pin TSOP II and
44-pin 400-mil-wide SOJ
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021B is available in standard 44-pin TSOP Type II
and 44-pin 400-mil-wide SOJ packages.
Functional Description
[1]
The CY7C1021B is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64K x 16
RAM Array
512 X 2048
SENSE AMPS
I/O
1
–I/O
8
I/O
9
–I/O
16
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document #: 38-05145 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 28, 2006