CY7C1019CV33-12VC Datasheet Download

Part No.:
CY7C1019CV33-12VC
Download:
Download Datasheet
Description:
[128K x 8 Static RAM]
File Size:
196 K
Page:
8 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C1019CV33-12VC Datasheet Page:1CY7C1019CV33-12VC Datasheet Page:2CY7C1019CV33-12VC Datasheet Page:4CY7C1019CV33-12VC Datasheet Page:5CY7C1019CV33-12VC Datasheet Page:6CY7C1019CV33-12VC Datasheet Page:7CY7C1019CV33-12VC Datasheet Page:8 
CY7C1019CV33
AC Test Loads and Waveforms
[4]
8-ns devices:
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Z = 50
10-, 12-, 15-ns devices:
3.3V
R 317Ω
30pF*
OUTPUT
30 pF
R2
351Ω
(a)
3.0V
90%
GND
10%
ALL INPUT PULSES
90%
10%
(b)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
5 pF
351
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
R2
Switching Characteristics
[5]
Over the Operating Range
7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU[8]
t
PD[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High
Z
[6, 7]
0
8
8
7
7
0
0
6
5
0
3
4
10
8
8
0
0
7
5
0
3
5
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
3
4
0
10
12
9
9
0
0
8
6
0
3
6
0
4
3
5
0
12
15
10
10
0
0
10
8
0
3
7
3
8
5
0
5
3
6
0
15
8
8
3
10
5
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle
[9, 10]
Notes:
4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05130 Rev. *D
Page 3 of 8