CY7C1019DV33-10ZSXI Datasheet Download

Part No.:
CY7C1019DV33-10ZSXI
Download:
Download Datasheet
Description:
[1-Mbit (128K x 8) Static RAM]
File Size:
387 K
Page:
11 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C1019DV33-10ZSXI Datasheet Page:2CY7C1019DV33-10ZSXI Datasheet Page:3CY7C1019DV33-10ZSXI Datasheet Page:4CY7C1019DV33-10ZSXI Datasheet Page:5CY7C1019DV33-10ZSXI Datasheet Page:6CY7C1019DV33-10ZSXI Datasheet Page:7CY7C1019DV33-10ZSXI Datasheet Page:8CY7C1019DV33-10ZSXI Datasheet Page:9 
CY7C1019DV33
1-Mbit (128K x 8) Static RAM
Features
• Pin- and function-compatible with CY7C1019CV33
• High speed
— t
AA
= 10 ns
• Low Active Power
— I
CC
= 60 mA @ 10 ns
• Low CMOS Standby Power
— I
SB2
= 3 mA
2.0V Data retention
Automatic power-down when deselected
CMOS for optimum speed/power
Center power/ground pinout
Easy memory expansion with CE and OE options
Available in Pb-free 32-pin 400-Mil wide Molded SOJ,
32-pin TSOP II and 48-ball VFBGA packages
Functional Description
[1]
The CY7C1019DV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019DV33 is available in Pb-free 32-pin 400-Mil
wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA
packages.
Logic Block Diagram
INPUTBUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CE
WE
OE
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
ROW DECODER
I/O
0
I/O
1
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
128K × 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com
Cypress Semiconductor Corporation
Document #: 38-05481 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised November 8, 2006