CY7C09269V-12AC Datasheet Download

Part No.:
CY7C09269V-12AC
Download:
Download Datasheet
Description:
[3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM]
File Size:
760 K
Page:
19 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C09269V-12AC Datasheet Page:2CY7C09269V-12AC Datasheet Page:3CY7C09269V-12AC Datasheet Page:4CY7C09269V-12AC Datasheet Page:5CY7C09269V-12AC Datasheet Page:6CY7C09269V-12AC Datasheet Page:7CY7C09269V-12AC Datasheet Page:8CY7C09269V-12AC Datasheet Page:9 
CY7C09269V CY7C09279V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
1CY7C025/0251
CY7C09269V/79V/89V
CY7C09369V/79V/89V
3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
Features
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
6 Flow-Through/Pipelined devices
— 16K x 16/18 organization (CY7C09269V/369V)
— 32K x 16/18 organization (CY7C09279V/379V)
— 64K x 16/18 organization (CY7C09289V/389V)
3 Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast
100-MHz operation
• 0.35-micron CMOS for optimum speed/power
High-speed clock to data access 6.5
/7.5
/9/12 ns
(max.)
3.3V low operating power
— Active = 115 mA (typical)
— Standby = 10
µA
(typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
Commercial and Industrial temperature ranges
Pb-Free 100-pin TQFP Package Available
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
LB
R
OE
R
FT/Pipe
L
I/O
8/9L
–I/O
15/17L
8/9
0/1
1b 0b 1a 0a
b
a
0a 1a 0b 1b
a
b
0/1
FT/Pipe
R
8/9
I/O
0L
–I/O
7/8L
A
0L
–A
8/9
14/15/16
I/O
Control
I/O
Control
I/O
8/9R
–I/O
15/17R
8/9
14/15/16
I/O
0R
–I/O
7/8R
A
0R
–A
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
CLK
R
ADS
R
CNTEN
R
CNTRST
R
Notes:
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices.
4. I/O
0
–I/O
7
for x16 devices. I/O
0
–I/O
8
for x18 devices.
5. A
0
–A
13
for 16K; A
0
–A
14
for 32K; A
0
–A
15
for 64K devices.
Cypress Semiconductor Corporation
Document #: 38-06056 Rev. *B
3901 North First Street
San Jose
CA 95134
• 408-943-2600
Revised April 6, 2005