CY7C037V-15AC Datasheet Download

Part No.:
CY7C037V-15AC
Download:
Download Datasheet
Description:
[3.3V 32K/64K x 16/18 Dual-Port Static RAM]
File Size:
237 K
Page:
18 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7C037V-15AC Datasheet Page:2CY7C037V-15AC Datasheet Page:3CY7C037V-15AC Datasheet Page:4CY7C037V-15AC Datasheet Page:5CY7C037V-15AC Datasheet Page:6CY7C037V-15AC Datasheet Page:7CY7C037V-15AC Datasheet Page:8CY7C037V-15AC Datasheet Page:9 
Pb
LEAD-FREE
CY7C027V/028V
CY7C037V/038V
3.3V 32K/64K x 16/18 Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow
simultaneous access of the same memory location
• 32K x 16 organization (CY7C027V)
• 64K x 16 organization (CY7C028V)
• 32K x 18 organization (CY7C037V)
• 64K x 18 organization (CY7C038V)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
Active: I
CC
= 115 mA (typical)
— Standby: I
SB3
= 10
µA
(typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• 100-pin Lead(Pb)-free TQFP and 100-pin TQFP
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
CE
L
CE
R
CE
0R
CE
1R
LB
R
OE
R
I/O
8/9L
–I/O
15/17L
I/O
0L
–I/O
7/8L
[2]
[1]
8/9
8/9
8/9
[1]
I/O
Control
I/O
Control
8/9
I/O
8/9L
–I/O
15/17R
[2]
I/O
0L
–I/O
7/8R
A
0L
–A
14/15L
[3]
15/16
Address
Decode
15/16
True Dual-Ported
RAM Array
Address
Decode
15/16
15/16
A
0R
–A
14/15R
[3]
A
0L
–A
14/15L
CE
L
OE
L
R/W
L
SEM
L
[4]
[3]
Interrupt
Semaphore
Arbitration
A
0R
–A
14/15R
CE
R
OE
R
R/W
R
SEM
R
[4]
[3]
BUSY
L
INT
L
UB
L
LB
L
Notes:
1. I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices.
2. I/O
0
–I/O
7
for x16 devices; I/O
0
–I/O
8
for x18 devices.
3. A
0
–A
14
for 32K; A
0
–A
15
for 64K devices.
4. BUSY is an output in master mode and an input in slave mode.
M/S
BUSY
R
INT
R
UB
R
LB
R
Cypress Semiconductor Corporation
Document #: 38-06078 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised September 20, 2004