CY7C008-20AC Datasheet Download

Part No.:
CY7C008-20AC
Download:
Download Datasheet
Description:
[64K/128K x 8/9 Dual-Port Static RAM]
File Size:
453 K
Page:
19 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7C008/009
CY7C018/019
Switching Characteristics
Over the Operating Range
[13]
(continued)
CY7C008/009
CY7C018/019
-12
[1]
Parameter
BUSY TIMING
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD[20]
t
INS
t
INR
t
SOP
t
SWRD
t
SPS
t
SAA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
5
12
5
0
11
12
12
12
10
5
5
15
12
12
12
12
5
0
13
15
15
15
10
5
5
20
15
15
15
15
5
0
15
20
20
20
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-15
Max.
Min.
-20
Max.
Unit
INTERRUPT TIMING
SEMAPHORE TIMING
Data Retention Mode
The CY7C008/009 and CY7C018/019 are designed with
battery backup in mind. Data retention voltage and supply
current are guaranteed over temperature. The following rules
ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during the power-up and power-down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (4.5 volts).
Timing
Data Retention Mode
V
CC
4.5V
V
CC
>
2.0V
4.5V
t
RC
V
IH
CE
V
CC
to V
CC
– 0.2V
Parameter
ICC
DR1
Test Conditions
@ VCC
DR
= 2V
Max.
1.5
Unit
mA
Notes:
19. Test conditions used are Load 1.
20. t
BDD
is a calculated parameter and is the greater of t
WDD
–t
PWE
(actual) or t
DDD
–t
SD
(actual).
21. CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not tested.
Document #: 38-06041 Rev. *D
Page 8 of 19