CY7B991V-5JC Datasheet Download

Part No.:
CY7B991V-5JC
Download:
Download Datasheet
Description:
[Low Voltage Programmable Skew Clock Buffer]
File Size:
529 K
Page:
13 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7B991V-5JC Datasheet Page:1CY7B991V-5JC Datasheet Page:2CY7B991V-5JC Datasheet Page:3CY7B991V-5JC Datasheet Page:5CY7B991V-5JC Datasheet Page:6CY7B991V-5JC Datasheet Page:7CY7B991V-5JC Datasheet Page:8CY7B991V-5JC Datasheet Page:9 
CY7B991V
3.3V RoboClock
®
Figure 2. Typical Outputs with Fb Connected to a Zero Skew Output Test Mode
[4]
t
0
– 6t
U
t
0
– 5t
U
t
0
– 4t
U
t
0
– 3t
U
t
0
– 2t
U
t
0
– 1t
U
U
U
U
U
U
t
0
+1t
t
0
+2t
t
0
+3t
t
0
+4t
t
0
+5t
FBInput
REFInput
1Fx
2Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
3Fx
4Fx
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
HH
– 6t
U
– 4t
U
– 3t
U
– 2t
U
– 1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
INVERT
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, allowing the
CY7B991V to operate as explained in the
level inputs can have a removable jumper to ground or be tied
LOW through a 100W resistor. This enables an external tester to
change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function select
inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
Note
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
Document Number: 38-07141 Rev. *D
t
0
+6t
t
0
U
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