CY7B994V-5AC Datasheet Download

Part No.:
CY7B994V-5AC
Download:
Download Datasheet
Description:
[High-speed Multi-phase PLL Clock Buffer]
File Size:
392 K
Page:
15 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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RoboClock
CY7B993V
CY7B994V
Table 1. Frequency Range Select
CY7B993V
f
NOM
(MHz)
FS
[2]
LOW
MID
HIGH
Min.
12
24
48
Max.
26
52
100
CY7B994V
f
NOM
(MHz)
Min.
24
48
96
Max.
52
100
200
[1:4]F1
Table 3. Output Skew Select Function
Function
Selects
[1:4]F0
and
FBF0
Output Skew Function
Feed-
back
Bank
Bank1
Bank2
Bank3
Bank4
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
–4t
U
–3tu
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
–8t
U
–7t
U
–6t
U
BK1
[3]
0t
U
BK2
[3]
+6t
U
+7t
U
+8t
U
–8t
U
–7t
U
–6t
U
BK1
[3]
0t
U
BK2
[3]
+6t
U
+7t
U
+8t
U
–4t
U
NA
NA
NA
0tu
NA
NA
NA
+4t
U
Time Unit Definition
Selectable skew is in discrete increments of time unit (t
U
). The
value of a t
U
is determined by the FS setting and the maximum
nominal output frequency. The equation to be used to
determine the t
U
value is as follows:
t
U
= 1/(f
NOM
*N).
N is a multiplication factor which is determined by the FS
setting. f
NOM
is nominal frequency of the device. N is defined
in
Table 2.
Table 2. N Factor Determination
CY7B993V
FS
LOW
MID
HIGH
N
64
32
16
f
NOM
(MHz) at
which t
U
=1.0 ns
15.625
31.25
62.5
N
32
16
8
CY7B994V
f
NOM
(MHz) at
which t
U
=1.0 ns
31.25
62.5
125
Table 4. Output Divider Function
Function
Selects
[1:4]DS1
and
FBDS1
[1:4]DS0
and
FBDS0
Bank
1
Output Divider Function
Bank
2
Bank
3
Bank
4
Feed-
back
Bank
Divide and Phase Select Matrix
The Divide and Phase Select Matrix is comprised of five
independent banks: four banks of clock outputs and one bank
for feedback. Each clock output bank has two pairs of
low-skew, high-fanout output buffers ([1:4]Q[A:B][0:1]), two
phase function select inputs ([1:4]F[0:1]), two divider function
selects ([1:4]DS[0:1]), and one output disable (DIS[1:4]).
The feedback bank has one pair of low-skew, high-fanout
output buffers (QFA[0:1]). One of these outputs may connect
to the selected feedback input (FBK[A:B]±). This feedback
bank also has one phase function select input (FBF0), two
divider function selects FSDS[0:1], and one output disable
(FBDIS).
The phase capabilities that are chosen by the phase function
select pins are shown in
Table 3.
The divide capabilities for
each bank are shown in
Table 4.
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
/1
/2
/3
/4
/5
/6
/8
/10
/12
/1
/2
/3
/4
/5
/6
/8
/10
/12
/1
/2
/3
/4
/5
/6
/8
/10
/12
/1
/2
/3
/4
/5
/6
/8
/10
/12
/1
/2
/3
/4
/5
/6
/8
/10
/12
Figure 1
illustrates the timing relationship of programmable
skew outputs. All times are measured with respect to REF with
the output used for feedback programmed with 0t
U
skew. The
PLL naturally aligns the rising edge of the FB input and REF
input. If the output used for feedback is programmed to
another skew position, then the whole t
U
matrix will shift with
respect to REF. For example, if the output used for feedback
is programmed to shift –8t
U
, then the whole matrix is shifted
forward in time by 8t
U
. Thus an output programmed with 8t
U
of skew will effectively be skewed 16t
U
with respect to REF.
Notes:
2. The level to be set on FS is determined by the “nominal” operating frequency (f
NOM
) of the V
CO
and Phase Generator. f
NOM
always appears on an output when
the output is operating in the undivided mode. The REF and FB are at f
NOM
when the output connected to FB is undivided.
3. BK1, BK2 denotes following the skew setting of Bank1 and Bank2, respectively.
Document #: 38-07127 Rev. *F
Page 5 of 15