CY7B991-2JC Datasheet Download

Part No.:
CY7B991-2JC
Download:
Download Datasheet
Description:
[Programmable Skew Clock Buffer]
File Size:
290 K
Page:
15 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY7B991-2JC Datasheet Page:2CY7B991-2JC Datasheet Page:3CY7B991-2JC Datasheet Page:4CY7B991-2JC Datasheet Page:5CY7B991-2JC Datasheet Page:6CY7B991-2JC Datasheet Page:7CY7B991-2JC Datasheet Page:8CY7B991-2JC Datasheet Page:9 
92
CY7B991
CY7B992
Programmable Skew Clock Buffer
Features
• All output pair skew <100 ps typical (250 max.)
• 3.75- to 80-MHz output operation
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at
2
and
4
input frequency
1
1
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50Ω while delivering minimal and specified output skews
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to
±6
time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to
±12
time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
Zero input to output delay
50% duty-cycle outputs
Outputs drive 50Ω terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Compatible with a Pentium™-based processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buff-
ers (PSCB) offer user-selectable control over system clock
Logic Block Diagram
TEST
Pin Configuration
PLCC/LCC
3F0
2F1
FS
FILTER
REF
FS
4F0
4F1
4
3F1
4Q0
SELECT
INPUTS
(THREE
LEVEL)
4Q1
V
CCQ
SKEW
3Q0
3Q1
SELECT
2Q0
MATRIX
2Q1
1Q0
1Q1
7B991–1
3
2
1
5
6
7
8
9
10
11
12
32 31 30
29
28
27
26
TEST
V
CCQ
GND
REF
FB
PHASE
FREQ
DET
VCO AND
TIME UNIT
GENERATOR
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
4F0
4F1
3F0
3F1
V
CCN
4Q1
4Q0
GND
GND
CY7B991
CY7B992
25
24
23
22
2F0
2F1
13
21
14 15 16 17 18 19 20
3Q1
3Q0
FB
2Q1
V
CCN
V
CCN
2Q0
1F0
1F1
7B991–2
Pentium is a trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07138 Rev. **
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised September 26, 2001